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@quantensalat dunno about standard chips. They may all try to protect against dc. But if you build one from scratch class d has no theoretical lower frequency limit. An #fpga can do it nicely.

@poleguy I was going to get a triangle wave and some comparators going, I've never heard of doing it with fpgas (sigma- delta?), thanks for the hint

@quantensalat @poleguy in an FPGA a triangle wave and a comparator becomes: a counter[1] and a comparator.
You don't even need to do Sigma-Delta.

[1] you can even could up and down which has some spectral benefits.

@hennichodernich @poleguy p.s . what's a good affordable board for beginners that can do the trick?

@quantensalat @poleguy This one's the lower limit, I'd suggest: https://www.reichelt.de/entwicklungsboard-artix-7-fpga-modul-cmod-a7-35t-digil-410-328-35-p243357.html

@hennichodernich @poleguy
Oops, a little bit more expensive than an Arduino :)

But am I missing something? I can't seem to find a mention of max. clock frequency anywhere in the daea sheet...
(or is "data rate up to 50mhz" that?)

@quantensalat @poleguy the achievable clock speeds are depending on the logic you're building combined with the propagation delays of the gates. 100MHz should definitely be possible.
Regarding the price: you could order a used EBAZ4205 from China, but it's SoC has an ARM core that should better be initialized at runtime. At that's another hoop to jump through for a beginner.

@hennichodernich @poleguy

Ok. now one more thing I would be gratetful to receive a hint about. Where do I find a good introduction and environment how to concretely program this thing (assuming that xilinx board) if all I know is a bunch of ordinary programming languages and the usual microcontrollers :)

@quantensalat @poleguy Digilent has good tutorials for their eval boards, see https://digilent.com/reference/programmable-logic/cmod-a7/start

@hennichodernich @poleguy I'm completely new to this so forgive my naive questions - do most people do high level c programming for these boards?

@quantensalat @poleguy Nope, high-level synthesis (HLS) is a niche application, mostly on high-end FPGAs. These smaller ones are usually "programmed" in Hardware Description Languages (HDLs) like VHDL or Verilog. Open-Source toolchains sometimes offer Python, but the intermediate language always is an HDL. (HLS also compiles into an HDL.)

@loic_fejoz @quantensalat @poleguy That's what I had in mind when I referred to Python, furthermore amaranth generates Verilog.
I would urge every beginner to start with the vendor-supplied examples before trying to set up an open source toolchain. There are already enough pitfalls there, you don't want to add additional ones.